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Chip Simulation Guidelines
This tiddler contains a list of points and checklist that is useful to follow when doing chip simulations.
- Top level simulation set must be a subset of the simulations done on the sub blocks of the system.
- Measure the ground current of Bandgap and other sensitive blocks and put layout notes on the ground line resistance to make ground drops less than 1mV.
- To do a DC sweep or an AC Sweep, it is better to do a transient sweep till everything settles down and then store the node voltages to a file. Load the file and then do the AC or DC sweep.
- When starting a transient ramp the Supply from 0 to help initial convergence quickly. Setting the Supply to a non zero value from t=0 may make the simulation longer by delaying the initial convergence.
- If at some temperature it appears to take a long time then try changing the temperature by 1-2 degrees
- In one simulation case simulate the circuit with a fast transient to see any high frequency instabilities in the system.
- Record all the model files with the simulation results. These are stored in case the models are changed so you have the original material intact to prove that your design was in compliance with the specifications.
- Simulate all EC Table parameters if possible.
- Do few worst case corners
- At top level add the bondwire RLC parasitics and simulate and monitor critical nodes for noise injection.
- Capture Critical nodes in SLOW power-up and power-down simulation
- Capture critical nodes in FAST power-up and power-down simulation
- Simulate all Test Modes and FT measurements to be made under those modes
- Simulate ESD zap on critical pins (HV or where ESD path is not very clear) when you use an active clamp as a protective device.
- Run checks to make sure no device is stressed for overvoltage
- Measure current in the reference ground and any other sensitive circuit ground to make sure its voltage drop <1mV
- Simulate Typical operating circuits given in the Design Review.
- Good operating supply range
- Failure supply voltage for the block and what failure happens
- All block level specifications (check the block level guidelines in notes)
- If chip has a high noise block like a switching large power FET then also do a simulation with a big noise on GSUB!/VIN and other nodes that may be shared before bond wires.
- Make list of simulations to do (Each and everything from the EC Table must be covered also each and every Final test setup must be covered to find out things like Dropout measurement on the chip.) To find the worst corners of a block start from the lower cells and work upto the block. Remember: Simulations done for higher levels should be a subset of lower levels. Lower levels should be simulated for all possible corners if possible.
- Do all simulations over all required corners and store results in excel sheets and keep a record of all the simulation result files plus the simulation netlists and simulation input files.
- Add any layout specific parasitics you know that will be there.
- Plan out failure simulations, where you worsen things that are normally not modeled properly to take the device to the edge of failure. These things being:
- MOS/Bipolar Parasitic capacitances
- Leakage currents for large EPI areas or any other reverse bias junctions.
- Create the simulation results EC Table in the Design Review Document
- Write Simulations for calculating the scaling factors of the EC limits in characterization.
- Do block level and if required system level simulations of leakage effects. Exaggerate the leakages and set temperature high to see the trend of behavior of the system and predict possible failure mechanisms. Document these things and keep ready for design review.
- Make detailed range analysis of trims and their percentage weights.