# Compensation Techniques

Here is a list and analysis of compensation techniques, that I have come across/used in my circuit design experience. Compensation can be used to:
• reduce noise (filter it off)
• make amplitude response flat
• make the amplifier stable for a particular feedback configuration

# Caution [top]

One thing to always keep in mind when doing compensation circuits is to not get carried away by just poles and zeros. Even if you get all the poles and zeros right and the amplifier bode plot looks very good the circuitry you may have added in the process may not be practical from a transient stand point. For example if you added a cap at a very high impedance point to make a dominant pole and the cap value you placed is so large that when that node needs to respond to a step it is very slow, then that solution may not be usable for compensating that design. Always check transient responses of compensated amplifiers and make sure they are stable and within specifications

# Dominant Pole Compensation [top]

This technique involves compensating by locating the dominant pole node and making it more dominant by loading it with more capacitance.

• Simple to implement

• Great deal of bandwidth loss

# Gain Compensation [top]

The gain of the amplifier is reduced so that loop gain bode plot moves down and gets stabilized. For an opamp circuit this can be done by decreasing the gm of the input differential pair. Or the Rout of the amplifier can be reduced, this will push the output pole also further which will be good if it is not the dominant pole.

• No bandwidth loss

This technique basically involves making a feedback network that introduces a pole and a zero in the loop gain but the zero is always before the pole. So this way the zero is placed on the non dominant pole of the amplifier to cancel it off and then the pole introduced by the network becomes the non dominant pole and since it is at a higher frequency the net effect is that the non dominant pole is moved further in frequency without effecting the dominant pole of the amplifier. Mathematically the loop gain is modified to include the following term:

`\$\$T(s) = {s-z_1}/{s-p_1}\$\$`

where Where `\$\$|z_1| < |p_1|\$\$`

A lead network to do this is shown below:

The technique can be best understood by considering the lead network circuit in a feedback system.

The loop gain equation is given as:

`\$\$Aβ=(R_G/{R_G+R_F})({R_FCs+1}/{R_G||R_FCs+1})(K/{(s+τ_1)(s+τ_2)})\$\$`

here the last term is the open loop opamp transfer function – modeled as a 2 pole system. So we see that if we make the zero \$(=-1/{R_FC})\$ equal to the non dominant pole `\$(=-1/τ_2)\$` then out non dominant pole would become `\$-1/(R_G||R_F C)\$` which is higher in frequency than the zero. Hence we have moved the non dominant pole higher up in frequency and stabilized the system. See a more detailed analysis in .

# Lag Compensation [top]

This technique involves placing a pole and then a zero successively much before the non dominant pole of the opamp comes. Since the pole comes first the magnitude response decreases compared to what it was before, also the phase response starts decreasing, when the zero comes the phase response is restored to what it was before as if the pole did not occur. This happens before the non dominant pole. So the net effect is that the non dominant pole sees the same phase response as before but a lesser magnitude response and so the magnitude response crosses the 0 dB line at a lower frequency thus stabilizing the opamp. Mathematically the loop gain is modified to include the following term:

`\$\$T(s) = {s-z_1}/{s-p_1}\$\$`

where Where `\$\$|z_1| > |p_1|\$\$`

A Lag compensation network is shown below:

To understand the technique look at the circuit:

`\$\$Aβ=(R_G/{R_G+R_F})(K/{(s+τ_1)(s+τ_2)})({RCs+1}/{{RR_G+RR_F+R_GR_F}/{R_G+R_F}Cs+1})\$\$`

The loop gain bode plot looks like:

Another way to do this is by the following schematic:

The transfer function of the above circuit is:

`\$\${g_mR_g}/2{sRC+1}/{(R_g+R)sC+1}\$\$`

So we see a pole is introduced before the zero and we have lag lead compensation. If the differential amplifier had been a fully differential one then also the network would result in lag lead compensation since then the transfer function becomes:

`\$\$g_m(R_{out}{||}(R+1/{sC}))=g_m{R_{out}(sRC+1)}/{(R_{out}+R)sC+1}\$\$`

A typical Lag Lead compensation frequency plot is shown below:

This plot has the pole at the 1KHz and the zero at 3KHz. The gain falls faster than before at 1KHz and the becomes parallel to the original at 3KHz at a lower level. While the phase response recovers fully as if the pole zero pair had not occurred.

## Design Tip [top]

As can be seen from the concept that the pole of the lag lead network should be placed much before the GBW of the loop gain before the addition of the network to be effective in increasing the phase margin.

## Circuit 1 [top]

When both lead compensation and lag compensation are used together the system is using Lead-Lag compensation. Mathematically the loop gain is modified to include the following term:

`\$\$T(s) = {s-z_1}/{s-p_1}{s-z_2}/{s-p_2}\$\$`

Where `\$\$|p_2| < |z_2|<|z_1| < |p_1|\$\$`

Example of such a circuit is:

The poles and zeroes for this network are given as:

`\$\$z_1=-1/{C_1R}, z_2=-1/{C_2R_F}\$\$`

`\$\$p_2={-(C_1(1+K)+C_2)+√{C_1^2K^2+2C_1K(C_1-C_2)+(C_1+C_2)^2}}/{2C_1C_2R}\$\$`

`\$\$p_1={-(C_1(1+K)+C_2)-√{C_1^2K^2+2C_1K(C_1-C_2)+(C_1+C_2)^2}}/{2C_1C_2R}\$\$`

where K is given as:

`\$\$K=R/{R_F{||}R_G}\$\$`

If we take some reasonable approximations as discussed in this article we can approximate the poles and zeros to:

`\$\$z_1=-1/{C_1R}, z_2=-1/{C_2R_F}\$\$`

The zeros are the same simple values. The poles are:
`\$\$p_1≈-1/{R_F||R_G(C_1+C_2)+RC_1}\$\$`

`\$\$p_2≈-{R_F||R_G(C_1+C_2)+RC_1}/{RC_1C_2R_F||R_G}\$\$`

If `\$C_2≪C_1\$` and `\$R≪R_F||R_G\$` then we can approximate the poles as:
`\$\$p_1≈-1/{R_F||R_GC_1}\$\$`

\$\$p_2≈-1/{RC_2}\$\$}}}

## Circuit 2 [top]

Another form that is called the Lag Lead network is:

`\$\$T(s) = {s-z}/{s-p_1}1/{s-p_2}\$\$`

Where `\$\$|p_2| < |z| < |p_1|\$\$`

Example circuit of this is (the same that we discussed for the Lead Network circuit 2):

The poles and zero of this network are given as:

`\$\$z=-1/{C_CR_C}\$\$`

`\$\$p_2={-(C_O+C_C)R_O-R_CC_C+√{C_C^2R_C^2+2C_CR_OR_C(C_C-C_O)+(C_C+C_O)^2R_O^2}}/{2C_CC_OR_OR_C}\$\$`

`\$\$p_1={-(C_O+C_C)R_O-R_CC_C-√{C_C^2R_C^2+2C_CR_OR_C(C_C-C_O)+(C_C+C_O)^2R_O^2}}/{2C_CC_OR_OR_C}\$\$`

If one time constant in the circuit is very dominant than the other then the poles can be approximated as:
`\$\$p_1≈-1/{(C_o+C_c)R_o+C_cR_c}\$\$`

`\$\$p_2≈-{(C_o+C_c)R_o+C_cR_c}/{C_cC_oR_cR_o}\$\$`

# Feedforward Compensation [top]

In this method a capacitor is connected across a amplifying stage to remove the stage at high frequencies to eliminate the pole created by that stage and reducing the gain.

# Dual Pole Compensation [top]

In this type of compensation 2 consecutive poles are introduced in the system at a very very low frequency i.e. . This then causes the gain to drop by 40dB per decade and it drops to 1 very soon without reaching to any significant frequency. The phase however is not 180 deg since that much phase shift due to 2 poles happens only at infinite frequency. So although the phase margin is very small maybe just a few degrees the system can never be unstable since it is free from any parasitic poles. One question can be what about ringing response. Since the Bandwidth and GBW of the system is so low, no visible frequency can pass through it so no ringing will be observed.

• Simple method
• Does not require attention to parasitic poles
• No ringing problem

• Can only be used for systems working for DC voltages
• Very slow response

# Miller Compensation [top]

In this type of compensation a capacitor is placed across a negative gain stage causing the miller multiplication of the capacitance on the input side making that the dominant pole.

Here if Rout2’ < Rout2 then the output pole is pushed further away. The miller cap acts as a short at high frequency thereby pushing out the pole. After compensation the equivalent circuit looks like:

Before Compensation the pole locations are:
`\$\$p_1=1/{R_{out1}C_1}\$\$`

`\$\$p_2=1/{R_{out2}C_2}\$\$`

After compensation the poles become (approximately):
`\$\$p_1=1/{R_{out1}(C_1+C_C(1+A_{v2}))}\$\$`

`\$\$p_2=1/{R_{out2}'(C_2+C_1)}\$\$`

where \$R_{out2}'\$ is the output impedance of the second stage when the output is shorted to its input. To see a detailed derivation of the above see here

Coming Soon Nested Miller Compensation

1. The book has good chapter on compensation analysis of multi stage opamps.
2. The book has a good chapter on different networks for compensating opamps