Design Reviews

27 August 2019 Link

Points to be well documented

  1. Power Up sequence
  2. Shutdown Sequence
  3. Layout floor plan and block specific layout guidelines
  4. Quantitative information sheets for each block and each transistor in those blocks
  5. Point of failure with respect to Supply and current
    1. Block Level
    2. System Level
  6. For each circuit block the headroom constrained branch and its worst case headroom requirement. Of course that has to be below the minimum operating supply voltage and even the lowest operating voltage which may be the UVLO falling threshold.

Data to be kept Handy

  1. Bipolar Beta graphs
  2. MOS gm/Id vs Id/(W/L) graphs

Handy Numbers

Bipolar Devices

  1. Variation in Is is around +/-30%. This translates to a variation of about +/- 2.5% in Vbe
  2. Beta can vary +/-15% over process.

MOS Devices

  1. Vth varies +/-20% to +/-25% about the typical.
  2. Vdsat varies +/-50% easily about the typical.


  1. Thin Film Resistors can vary +/-30% over the typical values.
  2. Poly Resistors can vary +/-15% over the typical values.


  1. Poly caps can vary +/-15% over the typical values.

Self Schematic Review Points

  1. Any spare or unconnected devices should have a good reason and a plan behind them to be there. For example spare mirrors should have a reason what current would you need to adjust. Spare transistors for putting circuit in shutdown should have a reason why they are already not connected.
  2. Bipolars anywhere? Consider carefully whether they can go into saturation especially during startup/shutdown and what happens then.
  3. What is the matching of each matched pair and mirror should be analyzed and numbers kept handy.