ESD Design

27 August 2019 Link

ESD Design for an IC

Main Guidelines

  1. Make a table of the ESD current paths for each pin combinations.
  2. For each path in the table make a list of the nodes it crosses and the worst case node voltage that the node may go upto.
  3. Check the circuit between each node combination if it can withstand that voltage. Things to keep in mind while doing that are high impedance nodes (unknown voltage level assume worst case), nodes set to some state during power off.
  4. If a circuit cannot withstand the voltage short the voltage by a low resistance path (in case of ESD event only) to shunt the ESD current, maybe by using diodes in a particular configuration or clamps.
  5. To analyze a suggested ESD scheme it is useful to draw the pins, the ESD cells and the immediate internal circuitry to the pin together with the ESD busses separately and analyze the paths.

Special Cases

  1. Large Power or Driver Transistors:
    1. When doing Power MOSFETs, usually they are so large that they are defined to be self protecting in the case of an ESD event, since they can handle the amount of current involved due to their large size.
    2. They come with huge Cgd and Cgs capacitances. Because of this the ESD event may go right through the capacitor to the pre driver section. So in case of large power MOSFETs make sure you are protecting your pre driver by say providing a current limiting resistance, or increasing its size or shunting it with capacitance or any such trick.
    The question now is how huge is huge? This should be answered by the ESD specification and the rise time for that specification.
    Eg. For max current of $1/10^{th}$ of 2kV HBM = 140mA and max dv/dt of 2000V/10ns=200e9V/s we have C=140e-3/200e9=0.7pF so anything greater than that can cause more than 140mA to flow.
    Another way can be to find the capacitive reactance for the ESD event. So slew rate is 200e9V/s this would correspond to a frequency slew rate as A 2 π f = 200e9 and for A=2000V, f=Slew/( A 2 π) and capacitive reactance = 1/(2 π f C). So for min $X_C=X_{CMIN}$ we have $C_{MAX}=1/{2 π f X_{CMIN}}=A/{Slew*X_{CMIN}}$ and any capacitance greater than or equal to $C_{MAX}$ will cause a problem for the predriver device that needs to be protected. Solving this for the above example $X_{CMIN}=2000/140mA=14.28K$, $C_{MAX}=2000/{200e9*14.28K}=0.7pF$ which is the same result as from the previous method.

System ESD

  • TIP: Fix he lowest rating Failure first and move up
  • Depends highly on the board layout, componet placement, spark gap locations
  • Causes a dip in the supply voltage
  • Care should be taken to protect the state of permantly latched flip flop states since they can reset and put the chip in another state.
  • Global signals should be bufferred locally and should be designed active low in the global route. For example a RB signal going to flip flops if it is global then during normal operation we want it to be high (i.e. designed active high) so on a supply glitch it goes down and then its timing will clear different flip flops. So its better to have a POR signal which is resetting using active high.

Also See

  1. Interconnect Reliability under ESD conditions
  2. Characterization, Modelling and Design of ESD circuits
  3. ESD Target Levels: Impacting ESD from Components to Systems
  4. Case for Lowering Component Level HBM/MM ESD Specifications and Requirements
  5. Case for Lowering Component Level CDM ESD Specifications and Requirements
  6. System Level ESD - Part I
  7. System Level ESD - Part II
  8. Wunch Bell Curve
  9. IC Design Steps