Input Pins: All pins where an externally generated signal is connected
Output Pin: All pins which is not an input pin, i.e. which does not connect an external source.
I/O Pin: All pins which can be configured as an Input or Output Pin.
Supply Pin: Where the Supply voltages are connected. These are the pins monitored for the Latchup current if the IC latches up.
Not Connected: These are the pins which are not connected in the Application.
All Input pins and I/O pins in input state or high impedance state are biased at their highest voltage in spec if they are not used for preconditioning the device. If the pins need to precondition the device then they are biased at the required voltage always.
All Output pins and I/O pins are left high impedance
On each pin a Voltage clamped (1.5x Abs Max voltage) Positive current pulse of 100mA is applied for a certain time (e.g. 5us rise, 5us fall and maybe 10us pulse) and removed. Part should not latch up.
On each pin a Voltage clamped (-0.5x max voltage) Negative current pulse of 100mA is applied for a certain time (e.g. 5us rise, 5us fall and maybe 10us pulse) and removed. Part should not latch up.
The Positive/Negative current stresses are reapplied after biasing the Input and I/O pins to their lowest voltage in spec. The part should not latch up.
After this the supply over voltage test is done where the supply pins are raised to 1.5x the Max supply voltage and the part should not latch up
After the stress the parts should also pass Production Test.
Any Diffusion that is connected to pad should have guard rings in the layout. Since any diffusion will get forward biased when that 100mA is pushed/pulled from it.
For making guard rings flawlessly and adequately refer the ESD cells in the process since ESD cells often connect diffusion to Pads and they have been designed properly to withstand Latchup.
Best to keep diffusions connected to pads close to the pads and further lines with current limiting resistors so that latchup design can be handled close to the pad.
