The MOS characterization test bench described here is the 1st thing I do when I am Getting Familiar with a Process. This setup allows me to get good idea about the device parameters as well as the matching. I use the data in my hand calculations to calculate the worst case headrooms, matching of mirrors and offsets of amplifiers.
We will run a DC sweep of the drain current and save the operating point for the whole sweep.
Create a text file and add the following:
save MN0:oppoint
Note here that MN0 should be a BSIM model device already. Sometimes it may be a subcircuit in that case MN0 should be replaced by MN0.mnbsim, etc.
Now save this file somewhere and include it in the Setup->Simulation Files->Definition Files list so that it gets included in the netlist
Now setup the variables as follows:
wid = Any width you want to characterize
len = Any Length you want to characterize
vgd = Gate to drain voltage can be set to 0 or any value if you want to simulate near triode regions or on the other end hot carrier effects
vbs = can be set to the Bulk Source voltage desired
ids = di*(TMP+273)/300 - if the current is to be PTAT in biasing otherwise just set it equal to di
di = average current to characterize
IDL = current for lower extreme measurement = dil*(TMP+273)/300
IDH = current for higher extreme measurement = dih*(TMP+273)/300
dil = <val> here <val> is the lower tolerance of di. If not PTAT then set it simply to <val>
dih = <val> here <val> is the higher tolerance of di. If not PTAT then set it simply to <val>
TMP = temp (if PTAT operation) or 27 (If absolute values of dil and dih need to be used
Now setup the DC sweep to sweep di from IDL to IDH.