Top Down Design Methodology

23 August 2019 Link

Notes from By Ken Kundert - The Designer's Guide to Verilog-AMS: 1st (first) Edition

Basic Rules

  1. Identify particular areas of concern in the design. Make plans on how to verify them in simulation and testing. Plans can be test benches with varying and specified levels of test bench block details and how to test them once the chip comes back and also how in final test. Planning process is important and should not be skipped.
  2. For simulation models do not write models that are more complicated than necessary. Start with simplest models and add features as needed only.
  3. Not necessary to model the behavior of a block outside its normal operating range instead add code to report them.

System Level Verification

  1. Choose an algorithm if needed using Math packages or block diagram simulators like Simulink etc.
  2. Now implement the algorithm closer to circuit blocks using models that model the interface behavior of circuit blocks.

Mixed Level Simulation

  1. After the system level is functioning. Some blocks are refined and transistor level circuits are designed for them. Now we can put in only those blocks in the system level simulation to test only those blocks right in the system.
  2. As the blocks are implemented as transistor level their original system level models can be improved so that when they are not in the system they are represented more accurately and thus give a better system simulation.

Final Verification

  1. SPICE simulation should be used together with mixed level simulation to verify the chip. SPICE should be used to verify certain top level cases where interfacing between the blocks is important. Start-up simulation is a good example.


  1. The test group can use the system design to design the tests