In this section I want to accumulate design issues for various blocks and circuits. Design process for production is mostly dealing and trading off with this factors.
ADCs
Flash ADC
Refer The Flash ADC on page 9- As the resolution is increased the number of comparators needed increase by a factor of 2. Thus area requirement increases a lot. One solutions to this is to use an interpolation ADC architecture as shown in the reference Figure 5, but that needs a diff pair with static power in the comparator architecture.
- The threshold steps reduce making the comparator input stages larger to reduce offset. If the comparator offset is larger than 1 LSB then the thermometer code is corrupted with a "bubble". This further makes the area requirement worse. It also makes the input capacitance much larger causing greater input loading and settling time.
- Larger comparator input stages cause larger kickbacks at sampling from internal comparator nodes. Some solutions are:
- Preceed the comparatgor input with continuous time diff amp - lots more power
- Reduce the resistor divider ladder network unit resistance - More power.
- The kickback currents ultimately flow from the reference buffers driving the resistor ladder so they should be made low impedance. More power dissipation.