IC Design Steps

27 August 2019 Link

A handy list of steps involved as a designer to define, launch, design, test and release new Analog ICs. The list has grown over the years and I still keep adding stuff in it. Comments/additions would be welcome!

Information Management Setup

The 1st step is to create a Information Organization structure on your computer. This is very important since the number of documents, measurements, specifications quickly get overwhelming and hard to keep track of.

Directory Structure

  1. Process Project Directory (To characterize different devices for the process, may be done in product project directory but update the process project directory also)
  2. Product Project Directory (This depends on your EDA tool and version control system but need to keep this information organized properly)
    1. Schematics
      1. Datewise Schematic Backups
    2. Symbols
      1. Corresponding to Schematics backup
    3. Simulation Data
      1. Copy the Netlist file with the simulation results file for reference. This is especially true if the process is new because the models evolve and change over time. Sometimes it becomes very hard to replicate previous simulations.
  3. Product Folder: Following Subfolders and the timeline and Schedule
    1. Design Documents: Following subfolders and schematics
      1. Market Definition: All documents related to Market Definition and Business Manager discussions
      2. Definition and Specification: Contains all documents pertaining to the definition and initial target specifications - Main document, graphs, drawings
        1. Simulation results: Any done for the IOS
      3. Design Review: All documents pertaining to the Design Review - Simulation Graphs, EC Table, Simulation results(Spreadsheet), ESD Files
        1. Die Size estimate calculations
      4. Design Notes: This directory generally contains my design spreadsheets, scanned or tablet written design journals. Simulation EC Tables and other working documents.
    2. Layout: Documents pertaining to Layout - Floorplan, Stream Files, Placement instructions, probe points list and coordinates
    3. Documents Referenced: Papers, other project Design Reviews, Process Files
    4. Bonding and Assembly: Bond Diagrams, Assembly Request Forms, etc.
    5. Bench Testing: Sample inventory directory, Sample Categorization charts, Readings, Graphs, Report
    6. Tapeout Documents: All documents submitted for Tapeout - Mask ECN, stream file, LVS and DRC reports, etc.
    7. Project Directory: Copy of the project directory after Tapeout.
    8. Testing and Wafer Sort
      1. QA Documents
    9. Datasheet
    10. Logistics: To contain tracking of all the parts received and sent etc.

Development Steps

Market Definition

Basic functionality needed by intended customer to be used very easily and tolerable limits should be decided at this stage.
  1. Do a chip feasibility Analysis. For this do the following:
    1. Read all the information provided carefully and check the basic things like:
      1. package possibilities currents and the bond wires needed plus the pins you would need, enough pins?
      2. Specs make sense e.g low shutdown current in a chip with large current? Leakages are higher.
      3. Spec limits mentioned are testable?
    2. Create a block diagram for the part functionality with the blocks that can be ported from other parts or created reasonably well. Create list of questions and get them answered so that the block diagram level is finished for the part.
    3. From the circuit complexity determine the critical points that determine the process requirements like voltage handling capability or speed requirements.
    4. Try setting specifications for each block: If cannot then assume some numbers. Create a list of critical questions about the specifications which might affect die size and/or process for the part. Get these answered so that you have idea of all critical specifications.
    5. Get overview of any special ESD robustness requirement.
      1. Clearly define the ESD objective and make sure the intended processes can support that.
      2. Define the target voltage (kV) and target specification (HBM, MM, IEC, etc.).
    6. Create a Die Size estimate for the part
    7. Create a list of required Wafer Sort and Final Test steps.
    8. Take All inputs (expectations) from the definer and the Business Manager:
      1. Estimated Selling Price for the part
      2. Wafer Cost for processes (intended processes should be listed out first)
      3. Wafer Sort and Test Cost estimates for the part.
      4. Packaging Cost.
    9. Discuss the above results during Market Definition and take inputs from everyone concerned.
  2. The Wafer cost of the process will determine the approximate cost of the chip depending on the die size.

Initial Target Specification

  1. System Architecture and Macro model
    1. Create a Block Diagram
    2. Set Specifications for individual Blocks
    3. Identify and record all issues for every block This comes out from:
      1. Market Definition
      2. System Level Simulation
      3. Previous Similar Project
      4. Chip behavior for conditions outside the specifications
    4. Pick out relevant blocks from other chips.
    5. Create a System level Macro model to simulate the design. Identify areas of concern and create a brief plan how to verify it in simulation, bench and final test.
  2. Select a Process (If not already decided in the Market Definition phase)
    1. Browse through the process. See Getting Familiar with a Process
    2. Simulate any critical specifications that need to be met in the process, get a reasonable idea on what might be achievable at what area cost.
  3. Look into ESD resources to see if specs meet and make a detailed ESD plan with ESD cookbook
    1. Include design of ESD protection in the Design Schedule
    2. Create the ESD Scheme for all the pins using the process or ESD guidelines.
      1. Assign ESD library protection cells with appropriate Absolute Maximum Ratings (AMR).
      2. Define safe ESD discharge path between every pin-to-pin combination.
      3. Create the ESD Path table and the ESD Cell schematic.
  4. Estimate the Die Size
  5. Look into packages that will be good for this - also depends on package testing capabilities of the Test group (e.g. does it offer Kelvin test at all temperatures or not). List out all possible packages with their associated costs.
  6. Create a layout plan of all the blocks and a preliminary Bond Diagram especially if the part uses large Power MOSFETs. This would give an idea of the bondwire parasitics to associate with the MOS right from the start.
    1. Keep in mind the issues listed in Step 1
    2. Add any other issues identified to the list
  7. Create a sample pinout.
  8. Finalize the EC Table
    1. Identify specs of concern and make a plan on how to verify and test them in simulation, bench and final test
    2. Each test adds a certain time. Normally the test cost estimate is given for 1s test time. Adding a voltage measurement increases test time by 7mS. (Confirm these numbers with the test engineer and be ready with cost adders at definition meeting.)
    3. Make sure all the spec limits are testable
  9. Create the Final Test and wafer sort Section
    1. List everything tested at Wafer sort with method (mini WS document) with the required pin conditions and method.
    2. List everything tested at Final Test with method (mini FT document) with the required pin conditions and method.
    3. List all parameters that will be Guaranteed by Design (GBD)
    4. Go through the Things to keep in mind for IC Final Test list.
  10. List out all required Road tests and Typical Operating Curves (TOCs) for the Datasheet
  11. List out all the Simulation Waveforms Application and Definer need to see in Design Review (DR).
  12. Write down the detailed description for the blocks and the chip functionality
  13. Create the Schedule
  14. Make definition document based on the above analysis, specifying closely what you will achieve
  15. Send the definition document out 1 week before at least to the Test Engineering.
  16. Create the Schedule and send it out to test for feedback and approval.
  17. Definition Meeting and submission
    1. Schedule the Definition meeting.
    2. Complete the Definition Action Items
    3. Send the document by email to all concerned for final review
    4. After approval ask for die type allocation
    5. Get the approvals and archive the document
    6. Get and fill out any cost analysis that needs to be done and submit to Business manager with schedule so that the project can be launched
  18. Study of Process in detail (2 days)
    1. Familiarize with all supporting docs
    2. Collect all matching data (Data Genie and Model Files)
    3. Go through all electrical specifications
    4. Refer to Getting Familiar with a Process


  1. Good idea to follow the Top Down Design Methodology as described By Ken Kundert - The Designer's Guide to Verilog-AMS: 1st (first) Edition
  2. Design all blocks simulating every corner for each block separately (NOTE: CORNER SIMULATIONS OF SMALLER BLOCKS SHOULD BE A SUPERSET OF CORNER SIMULATIONS OF UPPER LEVEL BLOCKS)
    1. Have hand analysis of
      1. Gain of every amp
      2. GBW Product of every Amplifier in feedback
      3. Offset of every diffamp
      4. Accuracy of every current mirror
      5. Accuracy of all important signals such as the bandgap voltage
      6. Headroom limits in every circuit
      Over the years I have developed a spreadsheet which does a lot of hand analysis for standard blocks for me taking basic device simulation data.
  3. Precautions and Guidance (Make a Caution List for the product, to keep watch all through the development cycle)
    1. Look up PU/PD issues with your circuit
      1. Find any high impedance nodes that might stray during power down.
    2. Look for Latchup sensitive areas of your circuit
      1. All I/O blocks - I/O defined as diffusion connected to Pad or to any node that basically can go above and below the supply rails and provide good amount of current.
      2. Specify gaurd rings for layout around any diffusion that is going to pad
      3. Refer Latchup Safe Design Tips
    3. Look up matching sensitive areas of the circuit and see if you are safe with mismatches
    4. Look up layout sensitive interconnects and components and add proper layout notes. See Layout Notes on Schematics for guidelines on layout notes.
    5. Look up design mistakes history and confirm that you are not repeating any
    6. Consult senior designers about your new topologies
    7. Always have a plan to layout any circuitry you design.
  4. Add Shutdown Circuitry to all the blocks if required
    1. Mark all the high impedance nodes in all blocks
    2. Make sure all high impedance nodes are set to a rail in shutdown.
  5. Metal Line widths
    1. Use the current rating of the wires as an initial estimate
    2. Separately route all high current carrying lines and connect them to pad using star connection.
    3. Mark interconnects whose layout resistance will be critical
      1. Measure current in the Bandgap ground or any critical voltage reference circuits and make sure its voltage drop <1mV with all the metal resistance.
  6. ESD and Latchup Design:
    1. Verify design has robust ESD discharge path for every pin-to-pin combination.
    2. Create ESD protection plan summary.
    3. Complete the ESD Pin Classification Form.
    4. Write layout notes for Latch-Up protection on devices going directly to pins.
    5. Review ESD Design
  7. Simulation Guidelines
  8. Pinout and Chip size Estimate
    1. Populate all cells in a layout and place them
  9. Do a DFMEA analysis to check for:
    1. Fire hazard conditions
    2. Any critical conditions that can be avoided
  10. Get a layout engineer to start working on the layout around 2 weeks before the Design Review.
  11. Make the Wafer Sort methodology and send it to the Wafer Sort Engineer
    1. List All test details (Make schematics if necessary)
  12. Make the Final Test methodology and send it to the test engineer.
    1. List All test details (make schematics if necessary)
    2. Decide the final test temperature
      1. If using a one time programmable kind of memory then keep in mind that at higher temperature the memory may be programmed weakly since the Ids is less of the floating gate transistor and hence less HCI current.
    3. Go through the Things to keep in mind for IC Final Test list.
  13. Create detailed plan of layout of critical circuits.
    1. Review the latchup guidelines for the process and add important latchup prevention notes.
  14. Do the write up of the design review document (Not necessary to include the sims, can be added in the week before the design review after sending out the "preliminary" DR document)
    1. Add layout plan of critical circuits.
  15. Review Caution List
  16. Update the floorplan completely.

Design Review

  1. In your copy of schematics mark all the offset contributions of different components in all diffamps or error contributions in all accurate circuitry
  2. Look at the Design Reviews points to have all information handy.
  3. Action Items and submit to Document Archive


  1. Reveiw Caution List
  2. Floorplanning
    1. All pads should be visualized as contacted by probes. Those visualised probes should not shadow any laser trim resistors.
    2. Check if there are any violations to the Laser Power adjust resistor placement and the Laser Focus placement
    3. Update metal widths for all lines now considering the resistance of the lines
    4. Get a preliminary bond diagram and get it approved
  3. Placement
    1. Visualize important analog signal routing and see noise or cross coupling issues
    2. Visualize Ground and supply routing and see noise or cross coupling issues
    3. After a block is placed insert at much spare things you can to utilize any possible space wastage.
  4. Routing
    1. Mark entry poins of VCC, GND and any other important signals on all blocks and based on those create a top level routing plan for those signals.
  5. ESD Layout Guidelines
    1. Verify all Bus resistances are under the expectations of the ESD cell proper functioning.
    2. Make sure the Layout is Latchup robust:
      1. Starting with pads highlight all points where the pad connects to diffusions through resistance lower than to cause low drop with 100mA current (JEDEC requirement to pass Latchup).
      2. Starting with that diffusions get the PNPN structure ending in another pad or supply terminal.
      3. Draw the parasitic SCR and identify the parasitic Bipolar bases and the biasing resistances. Lower Betas of the bases by adding a guard ring there (guard ring is actually a diffusion we give to the parasitic SCR but reverse the polarity from what was supporting latchup, so now the parasitic SCR does get a diffusion which is first of all a dummy diffusion and then it has reverse polarity) or reduce the biasing resistance by adding taps right at the base of the parasitic bipolar.
      4. Less Headache method would be to surround the diffusion connected to pad with appropriate guard ring always
      5. For any N diffusion (N-WELL) connected to GND and any P-Diffusion (P-WELL) connected to the supply should be guard ringed very well since its easier to fwd bias them and turn ON junctions that are close by.
  6. Bond Diagrams and their approval (Assembly form)
  7. If using laser trim components make sure to get laser/test plot approval
  8. Layout Checking
    1. Check for placement and orientation of MOS, Bipolar, Resistors
    2. Lines Routing
      1. Highlight matched pair lines and make sure the via structure and lengths match.
      2. Highlight high current lines
        1. Check for total line resistance seen by the current flow to current consuming devices. Check if vias and line widths are adequate (according to electromigration rules 㠴aken from Layout Design Rules Document).
        2. Check and mark appropriate point of entries of the top level lines into block.
      3. Highlight Supply and Ground lines for the block
        1. Check if any thin links are connecting big islands where more current may be required.
        2. Mark point of entry of the Supply and Ground lines for the block to get guidance for top level routing.
      4. Highlight high voltage lines and Metal 1
        1. Check if high voltage Metal 1 runs across
          1. EPI pockets
          2. P Wells
          3. P Active
          4. N Active
          If yes then the channel stops must be drawn i.e. p+/n+ rings with contacts around the wells
      5. Highlight Sensitive lines
        1. To reduce capacitance to other lines make separation from adjacent line 2x the width of your line
        2. Check if any noisy lines run close to sensitive signals such as bandgap
        3. Make sure they do not merge with high current lines to shift their levels.
        4. Review cross-coupled lines of a R-S latch. Make sure they do not run long or close to noisy lines since if they get a glitch and switch the latch it may be a bad error.
        5. Review the lines connected to NAND and NOR gates for the coupling induced in them. Example in a NAND gate with 2 series connected NMOS devices, if the lower NMOS is switching quite often the source of the upper NMOS is moving up and down with it coupling noise into the other signal, if we had placed this switching signal on the upper NMOS then the coupling would reduce since it has to go through the Cgs and then the Cgd of the lower NMOS.
    3. Check if metal lines overlap matched devices unsymmetrically - fix those.
    4. Highlight all Pocket node lines, NACT, CONTacts, Metal 1 and EPI pockets and check if adequate pocket taps are present.
    5. Highlight all PWELL node lines, PACT, CONTacts, Metal 1 and PWELLs and check if adequate PWELL taps are present.
    6. Highlight the EPI pockets in solid color (Different voltage EPIs in different colors) and highlight the P+ in a separate color (solid) to see if all the EPI pockets have a P+ channel stop drawn around them especially around high voltage pockets. Also highlight metal 1 to make sure all P+ channel stops have contacts on them wherever possible.
    7. For all I/O cells make sure they are Latchup safe. Review the Latchup prevention guidelines set by the ESD group.
      TOP LEVEL:
    8. Highlight all sensitive lines and try to group them together at maximum places and then run the group between supply/ground lines.
    9. Check lines overlapping blocks and check any possible coupling effect into block components if metal layers close. Make use of sparser routings in higher metals to separate the lines in a metal layer for minimum coupling.
    10. Check if metal lines overlap matched devices unsymmetrically - fix those.
    11. Highlight GSUB and make sure GSUB taps are present sufficiently across the chip and near all circuitry especially around circuitry connected to pads to prevent latchup.
    12. Highlight the ground lines one by one and make sure their pickups from blocks and resistance is fine. Calculate current through all ground lines and then decide on worst case resistance allowable in the lines.
    13. Highlight the supply lines and check their distribution to all blocks and whether they are entering the at the point of entries marked during block level review.
    14. Check for proper metallization thickness on ESD paths.
    15. Check power bussing to ALL blocks. Check bus width and # of vias used when bus is jumped.
    16. Check that blocks that need separate supplies are not shorted to other supplies.
  9. DRC
  10. LVS
  11. Reports generation:
    1. DRC
    2. Antenna Rule Check
    3. Assembly rule check
    4. Density reports
    5. LVS Soft
    6. LVS Hard
    7. XOR (if a die revision)
    1. Reticle Frame
    2. Beam
  13. Fracture and tapeout Data
    1. Check the fracture report to know how many die per wafer and show the die map.


  1. SLP checklist
  2. Generate Burn-In or DOPL Schematic (With ESD Pin Classification)
  3. Complete the ESD checklist for the part.
  4. Generate the DFMEA (Design Failure Mode Error Analysis) document if required.
  5. Wafer Allocation
    1. find out if the package assembly needs full wafer or cut will do? If full then allot wafer to be packaged
    2. allot wafer for your local assembly
    3. Wafer Start Request Form (WSRF) - Start the calculated number of wafers (Ask how many die needed for product release). NOTE: Lot number assigned in WSRF when the formed is signed off completely.
  6. Mask ECN (Attach documents)
    1. Reports
    2. Assembly form approved
    3. SLP checklist
    4. Reticle Map
    5. Wafer Map
  7. Archive Schematics (procedure on the CAD home page - Archive link)
  8. Maskview (Optional)

Post Tapeout Until Wafer Ship

  1. Create a bench testing plan and initiate any test board layout. For example if the test engineer is using a Kelvin socket and you need to correlate properly most likely you need a board with that kelvin socket for correlation. Get that started for layout and fabrication also. See Evaluation Board Design
  2. After a week or 2 start a Backup lot for the product (Optional - if confident product will work)
  3. When the wafer out date from the Fab is coming close (~2 months) update the Test and Wafer Sort Engineer on it.
  4. Attend the Wafer Sort TDR and Final Test TDR. Remember you have to duplicate the setups on bench for correlation.
    1. Carefully go through each test and its setup. (Check for any possible conflicts to interfere with the measurement targeted for a particular parameter)
    2. Things you should keep in mind for the TDR:
      1. All package information (Exposed pad or not, etc.)
      2. All Schematic connections.
  5. Decide how many wafers to put through sort/Assembly and FT, do not use all since that takes a lot of time. Just allot enough to have 5K units, with some margin so like 10K is a good number.

Testing Steps

  1. Get the wafer/samples
    1. Create a Bond Diagram for Local Assembly.
    2. Make sure you receive some samples for local assembly
    3. Receive wafer (from wafer dispatch) and get local assembled or ask sort engineer to do it for you.
    4. Bond diagram redone to get probe pads out if needed
  2. Bench Testing
    1. First of all do a "Wiggle" test - Test operation at various supplies and conditions to get an overview of all functionality and if everything seems to be working and what are the kinks that need to be investigated carefully.
    2. Create a Test plan
    3. Make a part organization system
      1. Store the parts carefully to repeat observations
      2. Associate observations with each sample (numbered with reference numbers) in a detailed excel sheet
    4. Go through the full EC Table and note all readings and verify all functionality, you will be asked again and again what you expected in the readings and what did you get, when the apps guy does his road test and the test engineer is getting his hardware ready.
    5. Create the full readings spreadsheet.
    6. Make sure for QA Burn In the Burn In board schematics are correct and setup is functional on bench (especially the packaged pin outs).
    7. Here is a checklist of all that should be done on the bench for evaluation:
      1. Bench Testing of the part
      2. Test Development/Correlation
      3. ESD Test
      4. Latchup Test
      5. Mini Burn-In
      6. Tester Temperature characterization
  3. Wafer Sort and Correlation
    1. After the sort engineer gets the Wafer sort done with the correlation units (min 10) ready, perform the correlation on the samples (min 3) locally assembled.
    2. During correlation look at the kind of sigmas you are getting for the 10 parts. Look for any anomalies and unexpected high sigmas and try to fix them now rather than in GBD stage since it may require correlation again.
    3. Follow up with the Product Lead Manager (PLM) and Wafer sort engineer to get the sort done on the decided quantity of wafers.
  4. Assembly
    1. Follow up with PLM to stay updated with the arrival of the assembled units.
    2. Get a correlation board ready with a plug gable socket. If Kelvin contacts needed make arrangements for a board to support that.
    3. Keep the Final Test engineer in the loop of the assembled units arrival, the FT program and hardware should be ready by that time.
  5. Final Test and Correlation
    1. After the assembled units arrive, do the test correlation on the parts.
    2. If the Test hardware is not ready then do a reverse correlation (Do your measurements and ship the units to the Test Engineer to correlate)
    3. During correlation look at the kind of sigmas you are getting for the 10 parts. Look for any anomalies and unexpected high sigmas and try to fix them now rather than in GBD stage since it may require correlation again.
  6. Limits and GBD Verification
    1. The units should be fully characterized. Characterize at least 150 units for proper sigma measurement. Work with the test engineer to refine the tests whose sigmas are large etc.
    2. Set EC Limits using the GBD sheet.
      1. When setting limits in summary be sure to look at sigma to be sure it makes sense. Do a histogram plot of the parameter to make sure it is a normal (Gaussian) distribution for sigma to make any sense.
    3. Discuss the GBD limits with Business Manager and Applications and get their approval if the Datasheet ECN meeting is already held or will be held later.
    4. GBD Verification is run by the test engineer. Ask the TE to collect all data at all temperatures to provide a copy to you so that if any limit change is requested later on you have the GBD Verification data to analyze the effect.


  1. After the FT program is ready and correlated, the FT engineer can provide serialized samples to the QA/ESD testing personnel.
  2. Make sure for QA Burn In the Burn In board schematics are correct and setup is functional on bench (especially the packaged pin outs).
  3. Verify the ESD Pin classification table is correct and is used for ESD testing.
  4. Also get the Latchup testing done, if the part is for automotive use then the latchup testing needs to be done at 125C for AEC qualification.
QA and Reliability is tested by the following tests.
  1. Latchup Testing
  2. ESD Testing
  3. PRECON - (Solder Reflow Preconditioning)
  4. DOPL Test - (Dynamic Operating Life)Burn in on application board at 125C with no humidity
  5. HALT - Burn in at 85C of the application board with 85% humidity
  6. HTRB - (High Temperature Reverse Bias Test). Reverse bias major power handling junctions of the device. Devices are operated in a static operating mode at or near maximum breakdown voltage and or current levels. PI Biases the pins at 80% of the maximum junction breakdown. Also the biasing has to be done to make it static.
  7. THBT - (Temperature Humidity Biased Test) - For non-hermetic packaged devices operating in humid environments. Accelerates the penetration of moisture through the external protective material. 85% RH at 85C. (PI runs at 100V rather than max voltage)
  8. HTSL - (High Temperature Storage Life) - Also called stabilization bake test. 150C or 175C.
  9. MSL - (Reflow Moisture sensitivity) - To classify the sensitivity of non-hermetic sold state SMDs to moisture induced stress so they can be properly packaged, stored and handled. The MSL Soak Requirements table shows the amount of moisture soak time according to the MSL level.
  10. HAST - (Highly Accelerated Stress Test) - HAST is performed for the purpose of evaluating the moisture resistance of on-hermetic packaged devices operating in high humidity environments. Bias is applied minimizing current draw using alternating potentials wherever possible. The test approximates a highly accelerated version of
the THBT test. These severe conditions of pressure, humidity, and temperature, together with bias, accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. 30°C, 85%RH, 18.6psig OR 110°C, 85%RH, 3psig


  1. Follow up on the road tests for the graphs to be included in the datasheets, the customer apps engineer should give a report on the tests.
  2. Review Datasheet manuscripts carefully and attend datasheet meeting.
  3. Attend and update the limits in the Datasheet ECN meeting.

Transfer to Production

  1. Transfer test hardware at the final assembly house
  2. Send a a qual lot to test and correlate with the main test hardware at test development. (This has to be done 3 weeks before to make sure enough time to correlate and debug the test hardware)

Fab Transfer

  • Test all the tests not tested in production testing like:
    • The thermal shutdown thresholds.
    • Bandgap TC i.e. the magic voltage



  1. Portable Power website (Product Development steps)
  2. Standard Products Website
  3. Document Control
  4. Evaluation Board Design